1. Field of the Invention
The present invention relates to a phase locked loop circuit, referred to hereafter as a PLL circuit, for producing an output signal with an oscillation frequency equal in magnitude to a multiple of the frequency of an input signal.
2. Description of the Prior Art
In general, a PLL circuit is used for producing a signal with a frequency equal in magnitude to a multiple of the frequency of an input signal referred to hereafter as a reference signal. The multiple frequency is also used for controlling the frequency of an oscillator. The frequency multiplication factor, that is, the ratio of the frequency of the signal produced by the PLL circuit to the frequency of the reference signal, is kept at a constant value even if the latter fluctuates. In other words, an output signal is produced always at a frequency equal in magnitude to a multiple of the frequency of the reference signal, faithfully following variations in reference-signal frequency.
Conventional PLL circuits of the type described above include the HD14046B series described on pages 103 to 106 of the "Hitachi CMOS Data Book" issued in March, 1983, by Hitachi, Ltd. A block diagram of the PLL circuit is shown in FIG. 11. Reference numeral 1 shown in the figure is a phase comparator for recognizing a discrepancy in timing between the rising edge of an input signal Pi as a reference signal, and a signal P.sub.FB output by a frequency divider 2 to be described in detail later. The phase comparator recognizes a timing discrepancy as a phase difference between the two signals. The phase comparator 1 outputs a signal P.sub.1 representing the difference in phase. The phase-difference signal P.sub.1 is smoothed by a filter 3, being converted into a direct-current voltage VCO.sub.in which also represents the difference in phase as well. A voltage-controlled oscillator 4 generates a pulse-train signal Po as an output of the PLL circuit. The train of pulses Po, which has a frequency proportional to the direct-current voltage VCO.sub.in output by the filter 3, is also supplied to the frequency divider 2.
Waveforms of signals appearing at a variety of points in the conventional PLL circuit described above are shown in FIG. 12. The principle of operation of the conventional PLL circuit is described in detail by referring to this figure. When the phase of the signal P.sub.FB output by the frequency divider 2 lags behind that of the input signal Pi serving as a synchronization reference by a period of time (a) shown in FIG. 12, that is, when the frequency of the pulse-train signal Po is too low, the signal P.sub.1 output by the phase comparator 1 increases in magnitude, indicating that the lagging phase of the signal P.sub.FB results in a positive difference in phase. This positive difference in phase, in turn, causes the direct-current voltage VCO.sub.in output by the filter 3 to be supplied to the voltage-controlled oscillator 4 also to rise as well. Accordingly, the frequency of the pulse-train signal Po output by the voltage-controlled oscillator 4 also increases. As a result, the phase of the signal P.sub.FB output by the frequency divider 2 is shifted forward.
As a result of the operation to shift forward the phase of the signal P.sub.FB output by the frequency divider 2 described above, on the other hand, the phase of the signal P.sub.FB output by the frequency divider 2 this time leads ahead of that of the reference signal Pi by a period of time (b) shown in FIG. 12, that is, the frequency of the pulse-train signal Po becomes too high. In this case, the signal P.sub.1 output by the phase comparator 1 decreases in magnitude, indicating that the leading phase of the signal P.sub.FB results in a negative difference in phase. This negative difference in phase causes the direct-current voltage VCO.sub.in output by the filter 3 to be supplied to the voltage-controlled oscillator 4 also to fall as well. Accordingly, the frequency of the pulse-train signal Po output by the voltage-controlled oscillator 4 also decreases. As a result, the phase of the signal P.sub.FB output by the frequency divider 2 is shifted backward. The operations to shift the phase of the signal P.sub.FB back and forth described above are repeated.
In this way, the PLL circuit forms a negative-feedback automatic control circuit with the signal P.sub.FB output by the frequency divider 2 used as a feedback signal for the reference signal Pi. As described above, the phase of the signal P.sub.FB output by the frequency divider 2 repeatedly lags behind and leads ahead of that of the reference signal Pi, resulting in positive and negative differences in phase alternately. While this operation is taking place, the two signals are finally brought to a synchronized state in which there is almost no difference in phase and, hence, nearly no difference in frequency between the two signals.
Let fi be the frequency of the reference signal Pi, fo be the frequency of the pulse-train signal Po output by the voltage-controlled oscillator 4, 1/n be the frequency-division ratio of the frequency divider 2 and f.sub.FB be the frequency of the signal P.sub.FB output by the frequency divider 2. In the synchronized state, fi=f.sub.FB. As a result, fo=f.sub.FB .times.n=fi.times.n, which implies that the pulse-train signal Po has a frequency n times that of the reference signal Pi.
An operation in a case that the reference Pi disappears due to some reasons is described as follows. Assuming that the reference signal Pi stops at a point (1) shown in FIG. 12. In this case, the signal P.sub.FB output by the frequency divider 2 is recognized by the phase comparator 1 to have a phase leading ahead of that of the reference signal Pi, that is, the frequency of the pulse-train signal Po is considered to be too high. The leading phase of the signal P.sub.FB causes the negative-feedback automatic control system to respond by making an attempt to shift the phase backward. Since the reference signal Pi has been stopped, another attempt is again made to shift the phase backward furthermore, causing the direct-current voltage VCO.sub.in output by the filter 3 or the voltage supplied to the voltage-controlled oscillator 4 to attain a lowest level in a short period of time. As a result, the voltage-controlled oscillator 4 outputs a train of pulses Po at a lowest possible frequency.
When the reference signal Pi is restored at a point (2) where the system is in an uncontrollable state, the signal P.sub.FB output by the frequency divider 2 is again recognized by the phase comparator 1 to still have a phase leading ahead of that the reference signal Pi. Thus, a request is made to shift the phase backward in spite of the fact that the direct-current voltage VCO.sub.in output by the filter 3 is saturated at the lowest level. At the next phase-comparison point, however, the signal P.sub.FB output by the frequency divider 2 is recognized by the phase comparator 1 to have a phase lagging behind that of the reference signal Pi, that is, the frequency of the pulse-train signal Po is considered to be too low for the first time since the stoppage of the reference signal Pi. Accordingly, the negative-feedback automatic control system responds by making an attempt to shift the phase forward in order to raise the frequency of the pulse-train signal Po.
In general, however, the filter 3 includes large integrating components. Accordingly, the direct-current voltage VCO.sub.in output by the filter 3 which has once been saturated rises slowly. It is not until the phase comparator 1 has compared the phases several times and a command to shift forward the phase of the signal P.sub.FB has been issued repeatedly that the direct-current voltage VCO.sub.in supplied to the voltage-controlled oscillator 4 finally attains the synchronized-phase level.
The PLL circuit can also be applied to power-control equipment such as an uninterruptable power supply and a reactive-power compensating apparatus. In the case of such a field of applications, the reference signal Pi is in general derived from the commercial power supply. The PLL circuit is, therefore, used to generate a signal having a frequency equal in magnitude to a multiple of the frequency of the commercial power supply. With a frequency divider having a frequency-division ratio of 1/360, for example, the frequency of the pulse-train signal Po output by the PLL circuit is 360 times that of the reference signal Pi. That is to say, if one period of the commercial power supply is 360 degrees, then one period of the pulse-train signal Po is 1 degree. By using the signal Po as a reference, the phase of the commercial power supply can thus be controlled at a resolution of 1 degree.
Power interruption occasionally occurs due to, among other things, the falling of a thunderbolt. Since the reference signal Pi is derived from the commercial power supply, the power interruption causes the reference signal Pi to disappear. In spite of that, the power control apparatus cited above is required to continue functioning as if the commercial power supply remained continuously available even if the commercial power supply serving as the source of the reference signal Pi is interrupted as is the case with the falling of a thunderbolt. It is also necessary to have smooth and shockless transition to the normal control operation at recovery from such power interruption even if the reference signal Pi is derived from the commercial power supply.
It is therefore necessary to devise a new PLL circuit applicable to such a control field, wherein a pulse-train signal Po can be output with the same oscillation frequency as that obtained in a synchronized state even if the reference signal Pi disappears. The problem of the conventional PLL circuit is that when the reference signal Pi becomes unavailable, an oscillation signal having a very low frequency inherent in the PLL circuit can merely be obtained.
In addition, the PLL circuit in general employs a filter comprising large integrating components. Accordingly, the filter remains in a saturated state entered at the removal of the reference signal Pi for a while even after the reference signal Pi is restored, being incapable of responding promptly. Moreover, the difference in frequency between the reference signal Pi and the feedback signal P.sub.FB is large at the time the reference signal Pi is restored. It is therefore not until the phase comparator 1 has compared the phases of the signals Pi and P.sub.FB several times and a command to shift forward the phase of the signal P.sub.FB has been issued repeatedly that the direct-current voltage VCO.sub.in supplied to the voltage-controlled oscillator 4 finally attains the synchronized-phase level.
As described above, the conventional PLL circuit has a problem that a state with unsynchronized phases is prolonged at the restoration of the reference signal a while after the stoppage thereof. This is because it takes time for the conventional PLL circuit to return to a synchronized state, wherein the two phases match each other, due to, among other things, the recovery timing of the reference signal Pi.